library ieee;
use ieee.std_logic_1164.all;

entity ps2_kb_phy_rx is
  generic (
    FLT_LEN : positive := 10
  );
  port (
    reset   : in std_logic;
    clock   : in std_logic;

    dev_clk : in std_logic;

    bit_rdy : out std_logic
  );
end entity ps2_kb_phy_rx;

architecture default of ps2_kb_phy_rx is
  signal filter_reg : std_logic_vector (FLT_LEN - 1 downto 0);

  signal flt_clk_reg : std_logic;
  signal flt_clk_nxt : std_logic;
begin
  flt_clk_nxt <=
    '1' when filter_reg = (filter_reg'range => '1') else
    '0' when filter_reg = (filter_reg'range => '0') else
    flt_clk_reg;

  process (reset, clock) is
  begin
    if reset = '1' then
      filter_reg <= (filter_reg'range => '0');
      flt_clk_reg <= '0';
      bit_rdy <= '0';
    elsif rising_edge (clock) then
      filter_reg <= dev_clk & filter_reg (FLT_LEN - 1 downto 1);
      flt_clk_reg <= flt_clk_nxt;
      bit_rdy <= flt_clk_reg and not flt_clk_nxt;
    end if;
  end process;
end architecture default;
